Potter et al. U.S. Pat. No. 6,444,563 discloses a method of making a ball grid array or chip scale package integrated circuit by first identifying the most unreliable solder ball joints on the integrated circuit. The worse case joints or joints in the vicinity of the worst case joints are changed in pad dimension and exposed to more ball/bump conductive material than the other more robust joints in the integrated circuit to create a ball on a larger pad that is larger than the normal size ball. The larger balls are formed by placing multiple smaller balls together on a single pad to form one large ball during a reflow operation. The larger ball improves the overall integrated circuit reliability by improving the reliability of the weakest joints in the integrated circuit design. The standoff of both the larger balls and the smaller balls are engineered to be substantially equal.
Stierman et al. U.S. Pat. No. 4,874,476 discloses a method of plating bumps on metallization on the face of a wafer, including the steps of placing the wafer in a transportable fixture wherein cathode needles press against the face of the wafer to make electrical contact and to force the backside of the wafer against a sealing member to prevent the plating bath from contacting the back side. The fixture with the wafer therein is placed in a cleanup or presoaked bath and is then transported to the plating bath without the operator having to touch the wafer. Stierman et al. recognized that when using TAB or flip chip technology, it is desirable that the bumps be tall, and further states the following. Studies involving computer stress modeling show that tall bumps give more stress relief and thus greater reliability than shorter bumps. The height of a well-formed bump is equal to the thickness of the photoresist on the face of the wafer. Since the depth of the via is equal to the thickness of the photoresist, it is apparent that deep vias produce tall bumps. The deep vias are more prone to trapping bubbles than are the shallower vias and the vias are on wafers being bump-plated by one of the prior art processes in which the wafers are either a vertical or face down orientation during plating.